1. Field of the Invention
The present invention relates to a data write control circuit formed in a semiconductor integrated circuit to write data such as a character font in a RAM and, more particularly, to a data write control circuit having a word length conversion function for converting data having a word length of 8 bits into data having a word length of 6 bits.
2. Description of the Related Art
Conventionally, in a computer system and the like, a semiconductor integrated circuit having a data write control circuit is used to write font data of characters to be displayed on a screen in a text video RAM. This data write control circuit writes data in a RAM 10 having 24.times.8 bits as shown in FIG. 1. This RAM 10 is constituted by a plurality of cell blocks 12a1 to 12c8 each for storing data in units of 8 bits (8 bits/word).
The above data write control circuit has a row decoder 14 for outputting row selection signals Ra1 to Ra8 for performing selection in the row direction of the RAM 10, a column decoder 14 for controlling selection in the column direction of the RAM 10, and three I/O gate blocks 18a to 18c which are selectively activated to input/output data in units of 8 bits with respect to the RAM 10. An 8-bit data bus 20 is commonly connected to the input sides of the I/O gate blocks 18a to 18c, and 8-bit data buses 22a, 22b, and 22c are connected between the RAM 10 and the output sides of the blocks 18a, 18b, and 18c, respectively.
In the data write control circuit having the above arrangement, in order to write data in a certain cell block (e.g., 12a1), the column decoder 16 selects and activates the I/O gate block 18a corresponding to the cell block 12a1. The row decoder 14 selects rows within a predetermined range in the row direction of the RAM 10, i.e., outputs a row selection signal Ra1. As a result, the data is written from the data bus 20 in the cell block 12a1 via the I/O gate blocks 18a and 22a.
According to the above arrangement, no problem is posed when, for example, character font data of a Japanese character (kanji) constituted by 16.times.16 dots as shown in FIG. 2 is to be written in the RAM 10. However, the following problem is posed when data of a character font in which the number of dots in the lateral direction (row direction) is smaller than the number of bits in the column direction of each of the cell blocks 12a1 to 12cn such as a Japanese character (katakana) constituted by 5.times.7 dots as shown in FIG. 3 or an alphanumeric character font is to be written in the RAM 10.
Assume that four characters each represented by character font data having 5.times.7 dots are to be continuously written in three cell blocks in each row (e.g., the cell blocks 12a2 to 12c2 in the second row) as shown in FIG. 1. Firstly, the I/O gate block 18a corresponding to the cell blocks 12a2 to 12a8 in the first column array is selected and activated by the column decoder 16. The row decoder 14 sequentially selects rows (seven times) within a predetermined range in the row direction of the RAM 10 (e.g., rows corresponding to row selection signals Ra2 to Ra8). In correspondence with this selection, seven 8-bit data (70H, 88H, 88H, 88H, F8H, 88H, and 88H) each obtained by adding three bits of "0"s to lower positions of 5-bit data in a corresponding row of character font data representing "A" are sequentially given from the data bus 20 to the I/O gate blocks 18a to 18c. In this case, since the I/O gate block 18a is selected and activated by the column decoder 16 as described above, these 8-bit data are written in columns of the cell blocks 12a2 to 12a8 via the I/O gate block 18a and the data bus 22a in correspondence with the above selection. In this manner, the character font data representing "A" is written. Note that in the RAM 10 shown in FIG. 1, each black square represents data "1", and each white square represents data "0".
Assume that a character font subsequent to the character font "A" is determined to be "B". In this case, since character font data representing "B" extends over two lower bits of the data bus 22a and three upper bits of the data bus 22b, the column decoder 16 selects and activates the I/O gate block 18a corresponding to the cell blocks 12a2 to 12a8, and the row decoder 14 sequentially selects rows within a predetermined range in the row direction of the RAM 10. In correspondence with this selection, seven 8-bit data (73H, 8AH, 8AH, 8AH, FAH, 8AH, and 8BH) each obtained by adding one bit of "0" indicating "empty" and data of two upper bits in a corresponding row of the character font data "B" to upper positions of the 5-bit data in a corresponding row of the character font data "A" are sequentially supplied to the I/O gate blocks 18a to 18c via the data bus 20. Therefore, in correspondence with the above selection, these 8-bit data are written from the I/O gate block 18a in columns of the cell blocks 12a2 to 12a8 of the RAM 10 via the data bus 22a.
Subsequently, the column decoder 16 selects and activates the I/O gate block 18b corresponding to the cell blocks 12b2 to 12b8 in the second column array continuous to the cell blocks 12a2 to 12a8 in the first column array, and the row decoder 14 sequentially selects rows within a predetermined range in the row direction of the RAM 10. In correspondence with this selection, seven 8-bit data (C0H, 20H, 20H, C0H, 20H, 20H, and C0H) each obtained by adding five bits of "0" s to lower positions of three lower bits of the 5-bit data in a corresponding row of the character font data "B" are sequentially supplied to the I/O gate blocks 18a to 18c via the data bus 20. Therefore, in correspondence with the above selection, these 8-bit data are written from the I/O gate block 18b in columns of the cell blocks 12b2 to 12b8 of the RAM 10 via the data bus 22b. In this manner, the character font data "A" and "B" are written in the cell blocks in the two continuous column arrays.
Character font data representing "C" is written in the same manner as described above, and character font data representing "D" is similarly written, thereby completing writing of the character font data "A", "B", "C", and "D".
As is apparent from the above description, therefore, in order to continuously write four characters each represented by character font data having 5.times.7 dots in three column arrays of cell blocks in units of 8.times.7 bits, a cycle of seven row selection operations must be performed for the cell blocks in the three column arrays twice per cell block, i.e., a write operation must be performed by 7.times.3.times.2=42 times. As a result, software processing for this operation is complicated, and a write processing time is prolonged.
In consideration of the above situation, a data write control circuit as shown in FIG. 4 is conventionally developed. This data write control circuit has, in addition to the arrangement of the data write control circuit shown in FIG. 1 described above, a system for processing data in units of 6 bits (6 bits/word). That is, this data write control circuit has four 6-bit I/O gate blocks 24a to 24d which are selectively activated by a column decoder 16 to input/output data in units of 6 bits with respect to a RAM 10, and an 8/6-bit selection controller 26 for selecting either the 6-bit I/O gate blocks 24a to 24d or 8-bit I/O gate blocks 18a to 18c. An 8-bit data bus 20 is commonly connected to the input sides of the I/O gate blocks 24a to 24d, and 6-bit data buses 28a, 28b, 28c, and 28d are connected between the RAM 10 and the output sides of the I/O gate blocks 24a, 24b, 24c, and 24d, respectively. When 8-bit data is input as data to be written in the RAM 10, the 6-bit I/O gate blocks 24a to 24d nullify two upper bits of the input 8-bit data and output the data to the data buses 28a to 28d. When 6-bit data is input as readout data from the RAM 10, the 6-bit I/O gate blocks 24a to 24d add two bits of "0"s to upper positions of the 6-bit data and output the data as 8-bit data to the data bus 20.
In the data write control circuit having the above arrangement, in order to write data of a character font representing a character constituted by 16.times.16 dots, as shown in FIG. 2, in the RAM 10, the 8/6-bit selection controller 26 outputs an activation signal of the 8-bit I/O gate blocks 18a to 18c (an inactivation signal of the 6-bit I/O gate blocks 24a to 24d). The column decoder 16 selects and activates the 8-bit I/O gate block 18a, and a row decoder 14 sequentially selects rows (16 times) within a predetermined range (e.g., rows corresponding to row selection signals Ra1 to Ra16) in the row direction of the RAM 10. In correspondence with this selection, data of the upper half (8 bits) in each row of the character font data representing the character shown in FIG. 2 is supplied from the data bus 20 to the 8-bit I/O gate blocks 18a to 18c and written in columns connected to the 8-bit I/O gate block 18a selected by the column decoder 16.
Subsequently, the column decoder 16 selects and activates the 8-bit I/O gate block 18b, and the row decoder 14 sequentially selects rows within a predetermined range in the row direction of the RAM 10. In correspondence with this selection, data of the lower half (8 bits) in each row of the character font data representing the character as shown in FIG. 2 is supplied from the data bus 20 to the 8-bit I/O gate blocks 18a to 18c and written in columns connected to the 8-bit I/O gate block 18b selected by the column decoder 16. In this manner, the character font data representing the character as shown in FIG. 2 can be written in the RAM 10.
A write operation in which four characters such as "A", "B", "C", and "D" each represented by character font data having 5.times.7 dots are to be continuously written in units of 8.times.7 bits is performed as follows. That is, the 8/6-bit selection controller 26 outputs an activation signal for the 6-bit I/O gate blocks 24a to 24d (an inactivation signal for the 8-bit I/O gate blocks 18a to 18c). The column decoder 16 selects and activates the 6-bit I/O gate block 24a, and the row decoder 14 sequentially selects rows (7 times) within a predetermined range (e.g., rows corresponding to row selection signals Ra2 to Ra8) in the row direction of the RAM 10. In correspondence with this selection, data of each row of the character font data representing "A" is supplied from the data bus 20 to the 6-bit I/O gate blocks 24a to 24d. In this manner, valid 6-bit data is output as write data from the 6-bit I/O gate block 24a selected by the column decoder 16 to the data bus 28a, and the character font data "A" is written in the RAM 10.
Subsequently, the column decoder 16 selects and activates the 6-bit I/O gate block 24b, and the row decoder 14 sequentially selects rows within a predetermined range in the row direction of the RAM 10. In correspondence with this selection, data of each row of the character font data representing "B" is supplied from the data bus 20 to the 6-bit I/O gate blocks 24a to 24d, and valid 6-bit data is output as write data from the 6-bit I/O gate block 24b to the data bus 28b, thereby writing the character font data "B" in the RAM 10. In this case, the write operation of the character font data "B" can be performed without adversely affecting the character font data "A" which is already written.
By sequentially writing the character font data representing "C" and "D" in the same manner as described above, the character font data "A", "B", "C", and "D" can be continuously written in the RAM 10.
As described above, this data write control circuit has two systems, i.e., a system corresponding to a word length of 8 bits and a system corresponding to a word length of 6 bits. Therefore, in order to continuously write four characters each represented by character font data having 5.times.7 bits in the RAM 10, a cycle of seven column selection operations need only be performed for each of the four characters, i.e., a write operation need only be performed by 7.times.4=28 times. Therefore, the number of write operations can be largely reduced as compared with that of the data write control circuit as shown in FIG. 1. However, since this data write control circuit requires two systems of gate blocks, i.e., the 8-bit I/O gate blocks 18a to 18c and the 6-bit I/O gate blocks 24a to 24d, and two systems of data buses, i.e., the 8-bit data buses 22a to 22c and the 6-bit data buses 28a to 28d, its circuit arrangement is enlarged, and a required wiring region is widened. Therefore, a chip size is increased when this circuit is incorporated in an IC arrangement.